1. Field of the Invention
The present invention relates to a technical field pertaining to semiconductor devices, and particularly to a semiconductor device having an insulating film with voids, and a semiconductor device manufacturing method characterized by a step of forming an insulating film having voids.
2. Description of the Related Art
A high-integration design has been required to be established for semiconductor devices, particularly LSI devices, and in order to satisfy this requirement, it is needed that wires to be connected to electronic circuit elements in the semiconductor device are designed in a microstructure, the intervals between respective wiring layers in a multi-layer wiring structure are reduced as much as possible and also the intervals between adjacent wires are reduced in the same wiring layer.
However, the microstructure design of wires reduces the distance between the wires, so that the capacitance between the wires is increased. Therefore, the transmission speed of signals to be transmitted through the wires is lowered, and thus the operation speed of the semiconductor device is lowered.
In order to avoid the above problems, it is necessary to suppress the increase of the capacitance caused by reducing the distance between wires. For this purpose, a method of lowering the dielectric constant of the insulating film located between wires has been utilized. In order to lower the dielectric constant of the insulting film, a method of forming voids (pores) in the insulating film has been proposed.
The following process may be used to form the voids in the insulating film. That is, an insulating film in which minute elusive portions made of a material having a relatively large etching selection ratio are dispersed into a base material having a relatively small etching selection ratio is formed, and then the overall surface of the insulating film is etched to remove the elusive portions and form the voids (pores). However, the etching process of this method could not bring an excellent effect if the elusive portions are adjacent to one another. Therefore, it is required to increase the occupation ratio of the elusive portions in the insulating film. However, this structure makes it difficult to obtain an insulating film having high strength. Further, it is impossible in this method to set the size, arrangement, etc. of the voids in a desirable style.
In another method of forming the voids in the insulating film, when the insulating film is deposited and formed by the CVD method or the like, voids are left on recess portions on the wire pattern forming surface serving as a base layer (Japanese Laid-open Patent Application No. Sho-62-188230, Japanese Laid-open Patent Application No. Hei-2-86146). However, according to this method, the voids can be formed only when a desired relationship is established among the distance between the adjacent wires, the film thickness of the wiring layer, the deposition condition of the insulating film, etc., and also it is difficult to set the size of the voids to a desired value. In addition, no void can be formed above the wires, and thus this method has no sufficient effect on the reduction of the capacitance between wires belonging to different wiring layers in the multi-layer wiring structure.
There is known another method of forming the voids in the insulating film (Japanese Laid-open Patent Application No. Hei-4-207055). According to this method, an insulating film is composed of a plurality of insulating layers. First, an intermediate insulating layer is formed on a lower insulating layer, windows are formed in the intermediate layer, and then the lower insulating layer is wet-etched through the windows to form pores between adjacent wires. Thereafter, an upper insulating layer is deposited and formed on the intermediate insulating layer, and the windows of the intermediate insulating layer are closed by utilizing the overhang based on the formation of the upper insulating layer, thereby forming voids between the adjacent wires. However, with this method, the material of the upper insulating layer invades into the pores between the adjacent wires through the windows during the period from the time when the deposition of the upper insulating layer is started until the time when the overhang of the upper insulating layer is formed on the windows of the intermediate insulating layer to close the windows by the overhang, whereby the material of the upper insulating layer is deposited on the substrate. Therefore, the voids formed between the adjacent wires are shallow in depth, and thus the effect of reducing the capacitance between the wires is lowered.